Semiconductor processing often involves the formation of components having varying voltage inputs in neighboring regions of a semiconductor wafer. For example, high-voltage components (e.g., transistors such as DMOS having voltages/currents up to 100V/2A) are formed in one region of the wafer, while lower-voltage components (e.g., CMOS and flash components) are formed in a neighboring region. In order to provide electrical isolation between one circuit and another on the wafer, semiconductor processing typically starts at moat formation, or shallow trench isolation (STI).
Initially, a surface of the wafer is substantially flat, wherein the wafer is typically coated with a nitride layer. An STI pattern is transferred to the nitride in the photolithography process, and the STI pattern is transferred into the silicon via an etch process, wherein trenches are formed in the silicon. The trenches are then filled with an oxide for electrical insulation (also called a “moat”). The oxide, however, not only fills the trenches, but also creates a layer of oxide over the entire surface of the wafer.
The wafer subsequently undergoes a polishing process, where the surface of the wafer is polished down to the nitride layer, wherein the nitride layer generally acts as a stopping layer for the polish process. Subsequently, the remaining nitride layer is then chemically removed. The CMP process, however, has a degree of selectivity associated therewith, wherein differing materials are polished at differing rates. For example, the rate at which the nitride layer is polished is slightly different than the rate at which the oxide is polished. Thus, while a planar surface is typically desired after the polishing, in reality, the surface not planar, but rather, a small step or ledge at the interface (or edge) between the moat (e.g., oxide) and active regions of the wafer is typically present.
After CMP processing, ion implantation processes are performed in order to form various doped regions in the active regions of the wafer. In order to implant ions into the respective active regions, photoresist layers are patterned over the wafer, wherein the photoresist generally prevents the ions from being implanted into non-selected regions. However, after implantation, achieved implant dosages and critical dimensions (CDs) associated with the photoresist have been found to vary significantly. In the past, such variations have been considered to be a matter or unknown “noise” in the process, and attempts have been made to control the variations by feedback systems that account for variations in photolithography tools, reticles, and combinations thereof for particular implant processes. However, variations in implant CDs can have deleterious results on device isolation parametrics, device performance, and production yields, especially as newer technology continuously moves to smaller and smaller device sizes.
In other semiconductor processing, BARC (bottom antireflective coating) layers are provided, wherein the BARC layers diminish CD variation. However, for ion implantation BARC layers cannot be utilized, since the BARC layer covers the whole wafer, and prevents the ion implantation implant from going through. Thus, an improved method for improving implant photoresist patterning CDs is desirable.